Fault - Tolerance in Multi - Computer Networks

Multi-computers connected in various architectures are now commercially available and are being used for a variety of applications. Some of the most commonly used architectures are the binary hypercube, the binary tree, cube-connected cycles, the mesh, and multistage interconnection networks. All of these architectures have the major drawback that a single processor or edge failure may render the entire network unusable if the algorithm running on the network requires that the topology of the network is maintained. The failure of a single processor or a link between two processors would destroy the topology of these architectures. Thus, some form of faulttolerance must be incorporated into these architectures in order to make the network of processors more reliable. While several fault-tolerance schemes have been proposed for specific architectures, these schemes are not general enough to provide fault-tolerance for other architectures. The goal of this thesis is to provide a more general approach that can be applied to several of these multi-computer network architectures with only minor modifications. A general scheme for constructing fault-tolerant multi-computer networks is proposed which uses switching networks to inter-connect the processors of the network. Two such switching networks are described in the thesis. The scheme can be used to provide k fault-tolerance with k spare processors. It compares favorably with other proposed schemes for fault-tolerant multi-computer networks, achieving higher reliability while using at most the same amount of extra hardware. A fault-tolerant multi-computer network constructed using the proposed scheme functions as if it was a non-redundant network. No extra control information is needed to ensure the fault-tolerant network functions properly. When a processor fails, the reconfiguring process can be initiated distributively. Fast context switching is provided to speed up reconfiguration. These properties